The diagram on this slide shows Intel®’s vision for a surveillance camera, using the FPGA as an SoC. The FPGA is at the heart of the WDR camera, capable of handling: the sensor interface which is glueless for parallel or high speed serial connectivity; the entire image sensor pipeline, or ISP; the unique image processing for WDR CMOS sensors (e.g. the Aptina MT9M033 WDR CMOS sensor); optimized motor control for pan and tilt; and on-chip video compression, scaling, analytics, Ethernet controllers, etc. No current ASSP or DSP can address the control and data pipeline required for the WDR sensors. Although this block diagram shows only an Ethernet connection, the FPGA can connect to off-chip encoders or PHY devices for the broadcast, analog, or IP (Internet Protocol) camera markets. Imagine using one PCB to connect to SDI, analog, or IP connections simply by board-level "stuffing" options and changing the FPGA design.