Assign Statement and it's examples - Part 9 of our Verilog Series

2024-03-06 | By DWARAKAN RAMANATHAN

What is an Assign statement, and why is it used?

In Verilog, the assign statement is used to explicitly assign a value to a wire or a net. It is primarily used for creating combinational logic, connecting inputs and outputs, and defining constants. Here's an explanation of the assign statement and why it is used:

Assigning Values to Wires or Nets:

In Verilog, wires (also called nets) represent connections between different parts of your hardware design. These connections can be used to transmit signals or values.
The assign statement is used to specify what value a wire or net should have at any given time. It essentially represents a continuous assignment, meaning that the value on the left-hand side is always equal to the value on the right-hand side.

Creating Combinational Logic:

The assign statement is often used to implement combinational logic, where the output depends only on the current values of the inputs.
For example, you can use assign to create a simple AND gate, like this:
In this case, the and_output wire is continuously assigned the result of the AND operation between input_a and input_b.

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assign and_output = input_a & input_b;‎

Connecting Inputs and Outputs:

In larger designs, you can use assign to connect inputs and outputs of different modules or blocks.
It simplifies the interconnection of various parts of your design and makes it clear how signals flow between them.

Defining Constants:

You can also use assign to define constant values that are used in your Verilog code.
This is useful for creating constants like clock dividers, delays, or any other fixed values that need to be used in your design.

Example:

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‎// Defining a constant using assign   
assign constant_value = 8'hFF; // An 8-bit constant with the value 255‎

Tri-state Buses:

The assign statement can be used to model tri-state buses or tristate buffers, where a wire can have multiple drivers.
Tri-state logic allows multiple modules to share a bus, with only one module actively driving the bus at a given time.

Example:

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‎// Tri-state buffer using assign  
assign bus = enable ? data_source : 1'bz; // When 'enable' is high, 'bus' gets ‎the value from 'data_source', otherwise, it's in a high-impedance state

Bus Concatenation:

You can use the assign statement to concatenate multiple buses or vectors together, creating larger data buses.
This is useful when dealing with multi-bit data and buses.

Example:

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‎// Bus concatenation using assign  
assign output_bus = {bus_a, bus_b, bus_c}; // Concatenates 'bus_a,' 'bus_b,' ‎and 'bus_c' into 'output_bus'‎

Conditional Assignments:

The assign statement can also incorporate conditional expressions to dynamically change the value of a wire based on certain conditions.

Example:

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‎// Conditional assignment using assign  
assign result = (condition) ? value_if_true : value_if_false;‎

Wire Delay:

In some cases, you might use the assign statement to introduce a delay in signal propagation. This can be helpful for synchronization or to model signal propagation time.

Example:

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‎// Introducing signal delay using assign  
assign delayed_signal = #1 input_signal; // Delays 'input_signal' by one time ‎unit

Latch and Flip-Flop Inference:

In certain situations, the assign statement can be used to infer latch or flip-flop logic based on the assignment conditions, although it's more common to use dedicated constructs like always blocks for sequential logic.

Example:

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‎// Latch inference using assign (not recommended)  
assign latch_output = (enable) ? data_input : latch_output;‎

It's important to note that while the assign statement is versatile, it is primarily intended for combinational logic. For sequential logic and more complex behavior, you typically use always blocks and flip-flops. The choice of whether to use assign or other Verilog constructs depends on the specific requirements of your design.

Examples:

AND Gate Module:

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module and_gate (  
input input_a,  
input input_b,  
output and_output );  
assign and_output = input_a & input_b;  
endmodule

OR Gate Module:

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module or_gate (  
input input_a,  
input input_b,  
output or_output );  
assign or_output = input_a | input_b;  
endmodule

XOR Gate Module:

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module xor_gate (  
input input_a,  
input input_b,  
output xor_output );  
assign xor_output = input_a ^ input_b;  
endmodule

2-to-1 MUX Module:

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module mux_2to1 (  
input select,  
input input_a,  
input input_b,  
output mux_output );  
assign mux_output = select ? input_b : input_a;  
endmodule

3-to-8 Decoder Module:

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module decoder_3to8 (  
input [2:0] input,  
output [7:0] outputs );  
assign outputs[0] = ~input[2] & ~input[1] & ~input[0]; 
assign outputs[1] = ~input[2] & ~input[1] & input[0];  
assign outputs[2] = ~input[2] & input[1] & ~input[0];  
assign outputs[3] = ~input[2] & input[1] & input[0];  
assign outputs[4] = input[2] & ~input[1] & ~input[0];  
assign outputs[5] = input[2] & ~input[1] & input[0];  
assign outputs[6] = input[2] & input[1] & ~input[0];  
assign outputs[7] = input[2] & input[1] & input[0];  
endmodule

Full Adder Module:

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module full_adder (  
input input_a,  
input input_b,  
input carry_in,  
output sum,  
output carry_out );  
assign sum = input_a ^ input_b ^ carry_in;  
assign carry_out = (input_a & input_b) | (carry_in & (input_a ^ input_b)); ‎endmodule

4-Bit Comparator Module:

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module comparator_4bit (  
input [3:0] input_a,  
input [3:0] input_b,  
output are_equal );  
assign are_equal = (input_a == input_b);  
endmodule

Priority Encoder Module:

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module priority_encoder (  
input [3:0] input,  
output [2:0] encoded_output );  
assign encoded_output = (input[3]) ? 3 : (input[2]) ? 2 : (input[1]) ? 1 : ‎‎(input[0]) ? 0 : 3'b111; // Default value for no inputs  
endmodule