Different ways to Instantiate a Module - Part 8 of our Verilog Series

2024-03-04 | By DWARAKAN RAMANATHAN

Introduction:

Delve into the fascinating realm of Verilog module instantiation, where we uncover the various approaches for connecting modules based on their ports. This blog breaks down the nuances of port-based module instantiation, including techniques like named association, positional association, and wildcard connection. Whether you're a hardware design novice or a seasoned engineer, this guide will equip you with the knowledge to effectively instantiate Verilog modules while managing their ports in your FPGA and ASIC projects.

Types of Instantiations:

In Verilog, module instantiation refers to the process of using one module within another. When instantiating modules, you need to connect the inputs and outputs of the instantiated module (referred to as the submodule) to the ports of the parent module. This can be done in various ways depending on your design requirements. Here are the different types of module instantiation with respect to ports:

Positional Association:

In this method, you connect submodule ports to the parent module's ports based on their order.
The order of connection must match the order in which the submodule's ports are defined in its module declaration.
It's a simple and straightforward way to connect ports but can be error-prone if the submodule has many ports, and you might forget the order.

Example:

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‎// Module instantiation with positional association  
submodule sub_inst (  
parent_input1, // Connects to submodule's port 1  
parent_input2, // Connects to submodule's port 2  
parent_output // Connects to submodule's output port  
‎);‎

Named Association:

In this method, you explicitly specify the connection between submodule ports and parent module ports by using their names.
This is more robust and less error-prone than positional association because it's easier to understand the connections, especially in modules with many ports.

Example:

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‎// Module instantiation with named association submodule sub_inst (  
‎.input_a(parent_input1), // Connects to submodule's input_a  
‎.input_b(parent_input2), // Connects to submodule's input_b 
‎.output(parent_output) // Connects to submodule's output 
‎);‎

Wildcard Connection:

This method uses wildcard connections, such as the .* operator, to automatically connect ports with the same names in the parent and submodule.
It's particularly useful when you have many ports with matching names, simplifying the instantiation process.

Example:

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‎// Module instantiation with wildcard connection submodule sub_inst (  
‎.*, // Automatically connects ports with matching names  
‎);‎

Parameterized Modules:

Verilog allows you to create parameterized modules, where you can pass parameters to customize the behavior of the instantiated module.
This is particularly useful for creating flexible and reusable modules.

Example:

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‎// Parameterized module instantiation  
submodule #(8, 16) sub_inst ( 
‎.input_a(parent_input1),  
‎.input_b(parent_input2),  
‎.output(parent_output)  
‎);‎

In this example, the submodule is parameterized with width parameters, allowing you to customize the input and output widths at instantiation.

Generate Blocks:

Generate blocks are used to conditionally instantiate modules based on certain conditions or parameters.
This is handy for creating modules that adapt to different configurations.

Example:

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‎// Conditional module instantiation using generate block  
generate  
‎  if (enable_submodule) begin  
‎    submodule sub_inst (  
‎      .input_a(parent_input1),  
‎      .input_b(parent_input2),  
‎      .output(parent_output) );  
‎  end  
endgenerate

In this example, the submodule is instantiated conditionally based on the enable_submodule parameter.
Array of Modules:

You can create arrays of modules, allowing you to instantiate multiple instances of the same module with different connections.

Example:

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‎// Array of module instantiation 
submodule sub_inst [3:0] ( 
‎.input_a(parent_input[3:0]),  
‎.input_b(parent_input[7:4]),  
‎.output(parent_output[3:0]) 
‎);‎

Here, you're instantiating four instances of the submodule in an array.
Hierarchical Instantiation:

In complex designs, you can nest modules within other modules, creating a hierarchical structure.
This allows for a modular and organized design approach.

Example:

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‎// Hierarchical module instantiation  
submoduleA subA_inst (  
‎.input(parent_input),  
‎.output(subA_output)  
‎);  
submoduleB subB_inst (  
‎.input(subA_output), // Connecting submoduleA's output to submoduleB's input ‎‎.output(parent_output)  
‎);‎

Here, submoduleA is instantiated within submoduleB.