During the converter’s start-up sequence, the voltage ramp is controlled as it rises to the output voltage. As shown here in the equation, a higher capacitance value will require a longer start-up time to handle a given current. High inrush currents are problematic and responded by the DC/DC converter as a fault condition. The power supply will protect the system and limit the current by tripping. In other words, the DC/DC Converter will either annoyingly disable itself then restart, or turn off its power MOSFETs and wait for the fault to recover. This cycle may repeat itself and the power supply may never reach the desired output voltage set point. Some FPGA rails may have a specific time window to successfully start up as shown in the FPGA data sheet. A soft-start time that is too long or too short may not meet the FPGA’s start-up requirement. Older FPGAs may require a monotonic start-up to address bus contention issues. DC/DC converters that have a well-controlled start-up wave form that does not slope negative are advertised with a monotonic start up.