If this is not desirable, the low power mode bits in the status register value that gets stored out on the stack need to be cleared. In this code example, the watchdog timer is being used as an interval timer and is creating an interrupt. When the first main loop instruction executes (setting the CPU OFF and GIE bits), interrupts are enabled by the GIE bit being set and the device goes into low power mode 0 because the CPU OFF bit is set. At this point, further code is not executed. The following X-or instruction is not executed and the MSP430 is in low power mode 0. When the watchdog timer interrupt occurs, the program counter and the status register (shown in this example as 0018) get pushed to the stack. The low power mode bits in the status register become clear and program execution continues inside of the interrupt service routine clearing the CPU OFF bit in the status register. When the RETI instruction is executed and the status register value is popped from the stack, the CPU OFF bit is no longer set. That leaves the MSP430 active for continuing code execution, and the X-or instruction is then executed in the main loop. After that, the jump instruction is executed and the 430 goes back into a low power mode. This example shows how to clear the low power mode bits that are stored in the status register value so that when exiting an ISR the MSP430 remains in active mode and continues code execution. Again, if the status register value is left alone on the stack, the MSP430 will go back into the prior low power mode after exiting the ISR.