FPGAs, ASICS, and other ICs demand increasingly tighter voltage regulation with larger current transients. This voltage budget problem is composed of three variables. The first is static variation, which is a function of the controller set-point accuracy, trim resistor tolerances, and other factors. With digital control, DLynx allows increments of 0.4% step changes in output voltage. The second is ripple and jitter. Selecting the appropriate level of output capacitance is easy with curves in the data sheet. The third, and most difficult, is transient response deviation. To demonstrate the increasing difficulty here, take an example of a 33 W load. Historically with 3.3 V and 10 A, a 50% load transient and 2% limit on transient deviation would have been 66 mV. Today, a 1 V load at 33 A with the same restrictions would require a maximum of 20 mV of deviation. At the same power level, new ICs demand less than 1/3 of the voltage deviation with over 3x the load transient. The DLynx solution is to use the Tunable Loop.