Device geometries dictate the power system level requirements. In other words, the techniques used at 90nm may not work properly somewhere between 65 and 45nm and they most certainly will not work as size reductions continue in lithography. Recall that as the leakage currents go up, the dark silicon issues arise (it is not possible to use everything on the die at one time). The device voltages decrease, the voltage accuracies increase, the need for sequencing and slew rate control on power up and power down become critical. Some of the new devices which have multiple cores have multiple device rails just for the processor itself. When the devices are implemented in combination with the other VLSI components needed to make a working system it becomes even more complex and critical. It would be simple to say that this is only an issue for high end super computers or systems which can afford complex power systems, however these devices are targeted for consumer electronics and general purpose embedded computing applications in a wide array of markets.