First some information from MIT and the University of California, San Diego, as presented in the SoCS session at the 2010 Hot Chips conference. In VLSI device design, power considerations are replacing die size and area as a more important constraint. As the geometries go down, the leakage currents go up at the device level. This is causing the need for power to take a higher design consideration at a systems level, at the beginning of the design process rather than the end. Device power utilization is changing the way companies design and build VLSI devices such as processors. However this is also being seen in memory, FPGAs, DSPs, SOCs, ASICs, I/O devices and more. The term “dark silicon” is used to define a wall in new devices where there is simply not enough available power to utilize all of the transistors in the device at the same time; thus more transistors will not give users greater performance. This wall is leading designers to consider several options to overcome this constraint. The key topic of this presentation is focused on more dynamic power management techniques at the system and task level – which is the best near term solution. Other options being explored are energy recycling on board the IC and stacked die, with wireless interconnects to construct devices. However, both of these approaches are exotic and expensive at this time.