One of the contributors to the new performance benchmark of these eGaN FETs is that they are in a chipscale Land Grid Array (LGA) package. This package format reduces board space, stray inductance, and parasitic resistance. However, due to the eGaN FET’s small size and pitch, greater care is needed during the assembly process than for larger, less efficient form factors. EPC has written an application note discussing how eGaN FET users can generally apply standard surface mount techniques to successfully attach the FETs onto standard PCBs. Also, for design engineers working in a lab environment wanting to mount devices quickly and reliably, a low-volume technique that has been demonstrated to be reliable and high-yielding is described. This application note can be found at www.epc-co.com. It should be noted that starting with the EPC2xxx series of products, there is a connection to the silicon substrate that has been brought to the surface. It is advised that the substrate be connected to source potential to get the maximum dynamic performance from the device.