This example depicts an integrated circuit PMOS that is lateral and symmetric in structure. D1 and D2 denote the two parasitic diodes that exist between the P material of the source and drain and the N bulk material of the substrate. Usually the PMOS bulk is directly connected with the highest potential which is normally V_IN. This configuration creates a parasitic path through D2 when V_OUT is greater than V_IN. The IC solution adds a bulk driver block selecting the higher of V_IN or V_OUT to make a bulk connection to the higher potential. This dynamic connection implements reverse current blocking when the switch is in the OFF state. This step accomplishes that of the back to back PMOS on the previous slide saving cost and improving the switch resistance.