For many applications, high performance is necessary to fulfill the critcal needs for many applications. AVR acheives this by incorporating: a true RISC architecture that reduces instruction complexity and provides faster execution; a Harvard architecture which allows code and data to be fetched in one clock cycle as the bus is not shared; true single cycle execution which provides one instruction executed per cycle on the external clock; and 20 MIPS at 20MHz is the maximum frequency for the standard AVR family generating close to 20 million instructions per second. The next generation XMEGA family offers 32 MIPS at 32MHz. The thirty-two general purpose registers are the heart of the AVR architecture and help to achieve very high performance by eliminating the traditional accumulator bottleneck. The register file can hold several 16- and 32-bit values at a time, ensuring a minimum penalty when working with larger numbers. For instance, a 32-bit add or subtract operation can be executed in just 4 clock cycles.