Intel® MAX® 10 leverages the available 32-bit Nios® II embedded soft processor to implement motor speed and position loops in software, as well as system configuration and management functions. Intel®’s Field Oriented Control (FOC) algorithm is implemented on the Intel® MAX® 10 FPGA fabric to accelerate performance, reduce latency and to off-load and free up the Nios® II processor for other tasks. The Intel® MAX® 10 FPGA fabric is also leveraged to implement the PWM and the encoder interface. Finally, that implementation is repeated multiple times and runs in parallel, to implement multi-axis control. Note, however, some significant enhancements that the Intel® MAX® 10 FPGA features bring to the DoC reference design: The entire design code for the Nios® II embedded processor and the rest of the FPGA now resides inside the configuration FLASH and user FLASH memory. The built-in ADC blocks make the ADC interface IP in the earlier designs a thing of the past.