Central to the motor control development framework is a software system based design flow targeting an integrated processor – either a soft CPU such as the Nios® II in the FPGA or the dual-core Cortex®-A9 in SoC Devices. Once modeled, the implementation can be partitioned into Software and Hardware functions where the HDL for the FPGA can be generated automatically and optimally by DSP Builder. Software is developed using standard IDE tools targeting the Arm® A9 or Nios® II. The processors, motor control functions and communication and power-stage interface functions are seamlessly integrated using the Qsys integration tool before compilation in Quartus® II. It is critical to note that the design methodology provides flexibility in how functions are partitioned across hardware and software. This is particularly valuable in targeting SoC FPGA devices where the choice to implement in software or hardware depends on a variety of factors including raw performance and realtime response requirements. For soft CPU based implementations where full offload to a DSP coprocessor in the FPGA for performance is not required, custom instructions for trigonmetric and floating point instructions can be very effectively used to accelerate soft CPU performance while maintaining all of the control completely in software.