Today‘s mid-range drive is typically a multi-chip solution: a high speed microcontroller and/or DSP for fast math-intensive computation, an ASIC for industrial networking, and a processor to do all the other interfacing and I/O. However, these drives typically run on a slow processor with fixed point control loops. They usually support a single axis. Flexibility of designs are primarily from software optimization. The trend for next generation drives calls for a more integrated solution; one that brings together the performance of an embedded processor and DSP blocks capable of floating point computation. PWM update rates being demanded are certainly greater than the capability of a microcontroller, and, beyond 40 kHz, beyond even the capabilities of DSPs. Competitive differentiation and cost pressures also requires this performance to be achieved at lower BOM costs, lower power consumption, and on-drive scalability to add motors in the same drive, and thus lowering the control cost per motor. With embedded processors, DSP blocks and on-chip memory, FPGAs are the ideal Drive-on-Chip platform to address performance and scalability challenges.