In this example, the C28x is the originator and the M3 is the receiver. It also assumes that the C28x has already written a message to either the shared message RAM or the IPC message registers, if needed. It should be noted that the interrupt itself could be a message with no extra data required. First, the C28x writes a 1 to a bit in the CtoM IPC set register; this could be in bits 0 through 3. If instead no interrupt was desired, bits 4 through 31 could be used. An interrupt is then sent to the NVIC and the M3. At the same time, the corresponding bit in the flag register and status register are both set. Remember that the flag register is on the sending side and the status register is on the receiving side. These bits indicate that a message is pending and has not been acknowledged by the receiver. The M3 reads the message, does what is asked and then writes to the ACK register to acknowledge. This will clear the flag and status bits. Note that the sending CPU can also clear the bit if desired using the CLR register; this does not, however, clear the interrupt from the NVIC or the M3, but simply clear the flag. For sending messages in the opposite direction, from the M3 to the C28, an identical set of resourced exists. The last IPC silicon feature this module will discuss is serial communication to perform IPC.