When the sending CPU wishes to inform the receiver that a message is ready, it can do so via either an interrupt or a flag; note that interrupts are not required. There are identical IPC interrupt and flag resources available on both the master and control subsystems. Each of the interrupts has a dedicated vector within PIE or the NVIC. Additionally, there 28 flags available to each of the subsystems. These flags can be used for messages that are not time critical or they can be used to send a status back to the originating processor; for example, a status could be sent describing if a message was a success or if it was not understood. The flags and interrupts can be used however the application sees for and are not tied to particular operations or hardware. The registers controlling the IPC interrupts and flags are all 32-bit. The low bits, 0 through 3, will force an interrupt along with a flag whereas the high bits, 4 through 31, force only the flag. The requesting, or sending, processor uses the set, flag, and clear registers. The set register is used to send an interrupt and set the flag; it can, however, be used to send only a flag if desired. The flag register indicates whether or not the set register has been used. It indicates if a message is pending and has not yet been acknowledged by the receiver. On the receiving side, the status register always reflects the flag register. The acknowledge (ACK) register is used by the receiving processor to acknowlege that a message was received and it will clear the flag. These registers are described in further detail on the next slide. Notice that register prefixes are used to indicate the direction of communication. For example, MTOCIPCSET would be master control. Likewise, CTOMIPCSET would be control to master. It is important to note from this slide that either the clear or acknowledge registers can be used to clear the flag and status bits. Normally, only acknowledge is used by the receiving CPU. Clear, however, may be used by the originating CPU in case of a timeout or if the sending processor does not need acknowledgement. However, note that clearing flags will not clear an interrupt. To continue, the next slide of this module will show an example of the C28x sending a message to the M3 using these registers.