This slide describes more in-depth how the address and data transfer successfully occurs in I²C communication. After the master sends the start signal, the master sends a 7-bit slave address, with the most significant bit leading. One bit is transferred per SCL clock cycle, making sure to only have a high to low or low to high transition on the SDA line when the SCL is held low. Additionally, since there are multiple I²C devices connected to the bus, the 7-bit address scheme is a unique and corresponding address for each I²C slave device. After this, the master then sends a read/write bit, and the corresponding slave device responds with an acknowledge bit. This acknowledge bit is signified as a low on the SDA line as the SCL is held high. The read/ write bit dictates what type of data transfer will occur. If the read/write bit is held high, then a read will occur where one or more data bytes will be transferred from the slave to the master. In contrast, if the read/write bit is held low, a write will happen where one or more data bytes will be transferred from the master to the slave. Once the data transfer action is complete, the master sends a stop condition.