A complete AD conversion consists of three components: an A/D conversion start delay time (represented by tD), a sampling time where the sample and hold capacitor is charged (this is shown as tSPL in the diagram) and finally the actual successive approximation time, (or tSAM), which is fixed at 30 clock cycles. When using a repeat mode the start delay only occurs for the first conversion in the sweep. The following channel conversion times are equal to the sample time plus the conversion time.