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This figure shows a typical block diagram of the 12-bit A/D converter in the RX/63N MCU. The block diagram for the RX62N is very similar but does not have the temperature sensor or internal reference power inputs. The multiplexed data inputs are highlighted by the red box. AVcc and AVss are the analog inputs that power the block while Vrefh and Vrefl are the reference inputs which drive the 12-bit D/A used in the successive approximation process. On the right side of the block diagram the internal data bus connection is shown along with the interrupt signal. The RX ADC allows an asynchronous trigger using the ADTRG (AD trigger) pin and also provides a synchronized trigger. The synchronized trigger is detailed later in this module. The RX ADC has various clocks which can be selected as the source for the AD clock including PCLK or PCLK divided by 2,4 or 8. Reference the HW manual for each specific device to determine which clock sources can be selected and for details on setting up the clock dividers. The block diagram also shows the individual conversion result registers (ADDR0 – ADDR20) and the various control and mode registers. In addition to the analog input data registers there are separate result registers for the temperature and internal reference conversions.
