Standard I2S ports typically support a single stream of digital audio containing the left and right data channels. Building upon the previous application example, it is possible to develop a 5.1 or 7.1 system by implementing the required clock, control, and data signals by using a number of slices and GPIO control. The LPC4300 series user manual provides an overview of a 5.1 audio channel implementation which provides master serial clock, an optional oversampling clock, three serial data signals, word select, and optional slave serial clock. In total, six slices are required for this communication interface. NXP has developed a demonstration system showing 7.1 audio capability using SGPIO to implement the I2S interface. In total, 7 slices are used for the 7 signals required. MCLK, SCLK and WS are loaded only one time, and are configured to repeat their patterns continuously until the data frames are complete. The CPU writes data to the SGPIO buffer register for each transmission word. Overall, the Cortex-M0 CPU load is estimated to be 5% at a 150 MHz clock rate.