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SRAM

In addition to separate power switches, each SRAM block in the LPC54100 has a separate bus to each of the cores. As a result, each core has its own SRAM block to avoid bus contention. For example, if you place Cortex-M0+ specific data into SRAM1 and Cortex-M4F specific data into SRAM0, both cores will be able to access the respective data in parallel without having to wait for the other to finish. The actual RAM placement is controlled by the linker definition file if using C or C++ programming language. If you are not able to separate memories for each core, the LPC54100 will continue to execute albeit at a slightly lower performance because of the bus arbitration that must be performed when two cores need to access same SRAM block simultaneously. Note that the flash memory is shared between the two cores – meaning that if both cores execute out of flash memory, one core will have to wait for the other to finish reading flash. Exact flash memory contention is reduced due to flash memory accelerator.

PTM Published on: 2015-02-05