The LPC54100 with its dual core architecture can reduce BOM cost and improve real-time performance. Many designs use two controllers to separate I/O handling, algorithm execution and communication stack. There may be several reasons for this approach, like reduce total power, execute compute-intense algorithm on a high-performance processor only or separate the time-critical or certified code from non-critical code. The LPC54100 with its asymmetric dual core architecture can eliminate the second processor, save power and cost. Designers can now use Cortex-M0+ core to manage I/Os and Cortex-M4F to execute algorithm and/or the communication stack. The LPC54100 can also be used to improve real-time performance. In a typical system where several events may occur very close to each other, the designer has to either find a faster processor or de-rate the system behavior. With the LPC54100, designers can divide event handling between two processors and manage events that may occur very close to each other.