Slide 1
Slide 2
Slide 3
Slide 4
Slide 5
Slide 6
Slide 7
Slide 8
Slide 9
Slide 10
Slide 11
Slide 12
Slide 13
Slide 14
Slide 15
Slide 16
Slide 17
Slide 18
Slide 19
Slide 20
Slide 21
Slide 22
Slide 23
Slide 24
Slide 25
Slide 26
Slide 27
Slide 28
Slide 29
Slide 30
Slide 31
Slide 32
Slide 33
Slide 34
Slide 35
Slide 36
Slide 37
Slide 38
Slide 39
Slide 40
Slide 41
Slide 42
Slide 43
Slide 44
Slide 45
Slide 46
Slide 47
Slide 48
Slide 49
Slide 50
Slide 51
Slide 52
Slide 53
Slide 54
Slide 55
Slide 56
Slide 57
Slide 58
Product List
Completing the list of analog blocks are the 10-bit DAC, POR and BOD. The 10-bit DAC features a resistor string architecture, buffered output, power-down mode, and selectable speed vs. power. The LPC17xx includes 2-stage monitoring of the voltage on the VDD (3.3V) pins. If this voltage falls below 2.95V, the Brown-Out Detector (BOD) asserts an interrupt signal to the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading the raw Interrupt Status Register. The second stage of low-voltage detection asserts Reset to deactivate the LPC17xx when the voltage on the VDD pins falls below 2.65V. This Reset prevents alteration of the flash as operation of the various elements of the chip would otherwise become unreliable due to low voltage. The BOD circuit maintains this reset down below 1V, at which point the Power-On Reset circuitry maintains the overall Reset.
PTM Published on: 2011-11-02