Simply put, the flash accelerator attempts to have the next Cortex-M3 instruction that will be needed in its latches in time to prevent CPU fetch stalls. Internally, the flash accelerator includes an array of eight 128b buffers to store both instructions and data in a configurable manner. The operations within this module are completely transparent to the end user. Programming this block is achieved by the “FLASHCFG” register alone. After reset, the flash accelerator defaults to the enabled state. Software can turn memory access acceleration on or off, or change the acceleration configuration at any time. Following reset, the flash access timing is also set to a default value of 6 CPU clocks. This is considered as a “safe setting” and will work for any condition. As an illustration, if the application needs to execute at 20MHz, the timing can be set to 1 CPU clock and if the application needs to execute at 100MHz, the timing can be set to 5 CPU clocks. Flash programming operations are not controlled by the flash accelerator, but are handled as a separate function.