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Product List
This diagram further elaborates on the clock system. Any of the 3 oscillators can be chosen to generate the SYSCLK. The main PLL and the CPU clock divider can then be used to generate the CCLK. The 8-bit CPU clock divider allows a range of options, including slowing CPU operation to a low rate for temporary power savings without turning off PLL0. Also as a note that when the USB interface is used in an application, CCLK must be at least 18 MHz in order to support internal operations of the USB subsystem. The peripheral clocks, PCLKS1-4, are derived from CCLK and there are 4 possible derivations - CCLK/2, CCLK/4, CCLK/8 or CCLK - which can be directly fed to the peripherals. Additionally, the peripherals have the option to select any of the four clocks, which offers the customer a lot of flexibility and helps the application to fine tune the power consumption. The clock for the watchdog can be derived from 3 sources: the Internal RC oscillator (IRC), APB peripheral clock (PCLK), and the RTC oscillator. The clock source selection can be locked by software, so that it cannot be modified. On reset, the clock source selection-bits are always unlocked. When the IRC is chosen as the watchdog clock source, the watchdog timer can remain running in deep sleep mode, and can reset or wakeup the device from that mode. The USB block has its own dedicated PLL which is designated as PLL1. If PLL1 is enabled, its output is automatically used as the USB clock source, and PLL1 must be configured to supply the correct 48 MHz clock to the USB subsystem. The USBCLKCFG register is used only if PLL1 is disabled and it controls the division of the PLL0 output before it is used by the USB subsystem. The PLL0 output must be divided in order to bring the USB clock frequency to 48 MHz with a 50% duty cycle.
PTM Published on: 2011-11-02