Now, let’s discuss the Memory Accelerator Module and the reason why it was created. Flash access time is approximately 50 nanoseconds. That limits execution with zero WAIT states to approximately 20 MHz. The need was to accelerate the execution out of Flash to be able to run at 60 MHz. To do this, the Memory Accelerator Module was created. Several key design objectives were required. One was to retain determinism. The clock cycles should be pre-determinable before runtime and countable by a tool chain. This is very critical in microcontroller environments because the designer typically wants a deterministic execution time, as opposed to something in comparison that had variable execution times. A cache memory would have multiple execution times depending on whether you get a cache hit or a cache miss. Another objective was to allow operation at 60 MHz with the 20 MHz Flash array. The intent was not to have any WAIT states in there. Lastly, cache was not used because it is difficult to implement. Cache performance is difficult to predict because you have multiple execution times, depending on whether you get a cache hit or a cache miss. In many applications, predictability, determinism, and repeatability are very important characteristics. Typically, cache takes a large portion of the real estate on a chip. Therefore, it is expensive to implement. For a low-cost device, cache is not desirable.