Here’s a block diagram of the PLL module. The source frequency, originating from either the crystal oscillator, the precision internal RC or an external clock is input to the pre-scaling divisor.  This pre-scalar can divide by 2 through 32, selectable by a parameter in a special function register. To allow the module to function properly, the output of the pre-scalar must be between 0.8 to 8MHz. This frequency then goes to a phase comparator driving a VCO. The output of the VCO is routed through a divisor that also drives the phase comparator. The value of this divisor corresponds to the multiplication factor of the PLL. The divisor can divide by 2 through 514, again selected by a parameter in a special function register. Note that the output of the VCO must be within 100 to 200MHz. The output of the VCO is routed to a post-scalar divider, which can divide by either 4, 8 or 16.