The EEPROM will not accept commands during a write cycle and therefore the master must wait until the write cycle is complete before sending the next command. ACK polling can be used to determine when the write cycle is complete. To do this, the master sends a starts bit and a control byte to the EEPROM, shown in the bottom of the illustration as control byte 1. If the EEPROM is still completing a write cycle, no ACK will be returned. The master continues to send the start bit and control byte until the write cycle is complete and the EEPROM sends the ACK bit back, shown as control byte ‘n’. The master can then proceed with the next command.