Microchip is bringing to market a stand alone Ethernet controller. The device comes with an on-chip 10 Mbps Ethernet Physical Layer Device (PHY) and Medium Access Controller (MAC), providing reliable packet-data transmission/reception based on an industry-standard Ethernet protocol. The PHY contains analog circuitry to encode and decode the data on the twisted pair interface while the MAC contains digital circuitry to control when to transmit, handle automatic retransmission when a collision occurs, calculate and validate CRCs (Cyclical Redundancy Check). A total of 8 kilobytes of RAM is present on the device. The microcontroller can configure how much of the 8kB is allocated to the receive hardware. The unallocated space remains useful as a transmit buffer. The Buffer memory enables an efficient method for packet storage, retrieval and modification, eliminating memory requirements for the host microcontroller. This buffer memory provides a flexible, reliable data-management system. One of the quite unique features for this Ethernet controller is that it interfaces to the Microcontroller over a Serial peripheral interface (SPI). With only 4 wires, a Microcontroller can be network enabled. It has two interrupts. One is general purpose interrupt, and the other, WOL or (Wake on LAN), allows a network administrator to send a packet and wake the device up from its sleep state.