Looking a bit closer, the figure here shows the high-level block diagram of the PSoC^™ 6 MCU. Most of the peripherals are available across all devices in the PSoC 6 MCU portfolio and a few select peripherals, like CAN-FD and audio peripherals are available only in select product families. The compute subsystem of the PSoC 6 microcontrollers consists of a dual CPU architecture with a 150MHz Arm^® Cortex^®-M4 and 100MHz Arm^® Cortex^®-M0+. The device has up to 1MB of on-chip SRAM and 1MB of on-chip Flash (with the option to expand the memory size with an external Quad SPI Flash interface). PSoC 6 supports fine grained low-power modes like active sleep, deep sleep, and hibernate; enabling optimization of power consumption. Even in active mode, two modes are available to trade off performance vs. power. The PSoC 6 integrates the 4th generation CAPSENSE^™ to integrate touch IC functionality in a single MCU along with standard peripherals like ADC/Timer/Counter/PWM, and I²C/SPI/UART. Select devices in the family also have audio peripherals, low-power analog block operation, SD host, or CAN-FD peripherals. The MCUs come in a wide variety of hardware packages suitable for space constrained wearable products to the home applications that require a low complexity, reduced layer PCB design and where packages like TQFP, QFN are preferred.