How are HYPERRAM^™ devices able to achieve this? This is enabled by the HYPERBUS^™ interface. This interface was developed in 2015 to facilitate a new memory architecture which enabled reduction in pin count without sacrificing on bandwidth required for high performance systems. Benefiting from the development of special protocol and clocking schemes with dedicated techniques for enhancing data integrity, the HYPERBUS interface can offer higher data throughput rates than legacy, and high-pin count parallel interfaces. In late 2017, the HYPERBUS became part of JEDEC as the JEDEC Expanded SPI (xSPI) interface. HYPERBUS utilizes a high-speed 8-bit I/O DDR interface for both address and data. In addition, it has an optional differential clock, a read/write latch signal, and a chip select for each memory device. HYPERBUS allows an external Flash and RAM to be connected on the same bus and works with any microcontroller supporting a HYPERBUS compatible interface. In total, twelve control and data signals are utilized to transfer data including one chip select pin. HYPERRAM is a self-refresh DRAM product supporting the HYPERBUS interface. NOR Flash products supporting the HYPERBUS interface are called HYPERFLASH^™ memories. The HYPERRAM product family also has products supporting the Octal xSPI standard and these memories are called Octal xSPI HYPERRAM. The ball out diagram on the right, shows the common footprint shared by both HYPERRAM and HYPERFLASH with the requirement of only one additional chip select pin to communicate on the same HYPERBUS. As mentioned, both the HYPERBUS as well as the Octal xSPI interface are JEDEC compliant. Both profiles support an identical, x8 DDR physical layer but with slight differences in their command/address frames.