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Image of Infineon Technologies HYPERRAM™ 2.0/3.0 Family - HYPERRAM Architecture

HYPERRAM™ devices have DRAM arrays with self-refresh circuitry. The Generation 2.0 devices support an 8-bit Octal xSPI or HYPERBUS™ interface and the Generation 3.0 devices support a 16-bit wide extended version of the HYPERBUS interface.

PTM Published on: 2023-11-22