This graphic examines the CryptoMemory® and CryptoRF® Chip architecture. The memory array is surrounded by the cryptographic logic, which employs a 64-bit hardware encryption engine to support both mutual authentication and encryption. The memory array is divided into two sections: the user memory and the configuration memory. The user memory section is segmented into independently configurable zones. There are 4, 8, or 16 zones depending on the overall user memory density desired. The configuration memory is where the multiple keys, passwords, and security level preferences are defined for each zone. Multiple hardware tampers are onboard to provide additional protection.