All Microchip AVR® UC3 microcontrollers are modern communication hubs, and allow users to increase data throughput. All the devices contain a multi channel peripheral DMA controller that drives communication in all interfaces at maximum speed, eliminating the slower CPU interrupts from the high-speed communication. Some AVR UC3 devices even contain the innovativ Microchip Peripheral Event System, which connects multiple peripherals together for synchronized, autonomous operation without CPU intervention. This removes interrupt latency and jitter from the application. The Peripheral Event System is extended into the sleep modes where a peripheral can choose to wake up the system upon a qualified input—like a TWI address match. To ensure the CPU and peripheral DMA controller can access the SRAM without collision, the AVR UC3 uses a dual-port SRAM that can be accessed by both simultaneously. For some devices, this is further improved by distributing extra SRAM blocks near high-speed communication interfaces that can be used as a dedicated buffer in applications where throughput is of the essence. AVR UC3 devices contain up to eight parallel high-speed data busses connecting high speed memories and DMA controllers. This eliminates bottlenecks in the user’s application.