Here is a conceptual drawing showing the architecture of a typical MAX® 10 FPGA device. The customer will see the device has a columnar structure with Logic Array Blocks, RAM blocks, and DSP blocks organized vertically up and down the die. Depending on the density device selected, there are 6 or 8 I/O banks around the periphery of the die, with multiple banks per side offering more choices for different I/O support per device. The I/O can interface to a variety of different voltage levels and I/O standards. The analog blocks in the left side of the die, depending on the density and package option selected will get one access to 1 or 2 ADC blocks. The Configuration Flash Memory and User Flash Memory are also in the left hand side of the die. Internal configuration memory has numerous customer benefits over devices that require an external configuration device such as, faster startup time, less board space, and a smaller bill of materials. Another customer benefit of internal configuration storage is increased security because there are no exposed programming interfaces and therefore no way to intercept a configuration bit stream coming into the FPGA. Also, the on-chip FLASH is NOR type memory which is much more reliable than NAND type memory. On the larger density device members, 10M16 – 10M50, there is support for main-stream external memory interfaces: DDR3, DDR2 and LPDDR2. Interfacing to legacy external memory, SRAM, is available on every member of the family. Finally, various kinds of soft IP cores can be added to the FPGA design including the Nios® II 32-bit processor or a memory controller for the external DRAM devices.