Although SPI is known as a four wire serial bus with slave or chip select (CS), SPI was initially a three-wire protocol consisting of two data lines and one clock line. Due to the demands for higher throughputs in embedded designs new multi-lane protocols have been introduced to improve the performance. Dual SPI is when full duplex mode is not required, both data pins can be used in a half-duplex configuration to send two bits per clock cycle. Usually the MOSI line is used to carry even bits while the MISO line carries odd bits. Dual read commands accept the send and address from the master in single mode, and return the data in dual mode. Quad SPI adds two more I/O lines (SIO2 and SIO3) and sends 4 data bits per clock cycle. This is requested by special commands, which enable quad mode after the command itself is sent in single mode. Octal SPI adds four more data lines. DDR or Double Data Rate transfers data on both the rising and falling edges of the clock signal. Finally, QPI is a mode where all communication takes place over 4 data lines, including commands.