The master sets the clock polarity and phase with relation to the data and the timing diagram as shown here. Clock Polarity and Phase (CPOL) determines the polarity of the clock. The polarities can be converted with a simple inverter. CPOL=0 is a clock which idles at 0, and each cycle consists of a pulse of 1 or the leading edge is a rising edge, and the trailing edge is a falling edge. CPOL=1 is the inverse and idles at 1. CPHA determines the timing of the data bits relative to the clock pulses. For CPHA=0, the output side changes the data on the trailing edge of the preceding clock cycle, while the input side captures the data on the leading edge of the clock cycle. The output side holds the data valid until the trailing edge of the current clock cycle. For the first cycle, the first bit must be on the MOSI line before the leading clock edge. For CPHA=1, it is the inverse. The MOSI and MISO signals are usually stable for the half cycle until the next clock transition. SPI master and slave devices may well sample data at different points in that half cycle. This adds greater flexibility to the communication channel between the master and slave. The combinations of polarity and phases are often referred to as modes with CPOL as the high order bit and CPHA as the low order bit. Most common mode is mode 0 or CPOL = 0 and CPHA = 0.