Slowing the slew rate on the edges of the clock signal is the quickest method to reduce EMI. This figure shows a scope shot of the same clock output with four different drive strengths. The signal slew rate changes proportional to the drive strength change. The Si512xx timing devices allow four levels of programmable drive strength for each output independently, consequently allowing board designers to customize each output according to load and trace length. With other clock vendors, slew rate control typically applies to the entire bank of outputs. Therefore, if one receiver requires a fast edge rate, all other receivers driven by the same output bank will have that same fast slew rate, resulting in higher EMI.