The complexity of the clock tree and the number of clocking components used depends on the hardware design. A basic clock tree example is shown here in the Before and After diagrams. In the diagram on the left, the FPGA clocks are provided by single output XO oscillators, while a 25 MHz crystal oscillator frequency is generated for the GbE Ethernet PHY. This clocking design will require more board space and more parts on the BOM. The After diagram illustrates using a SiLabs Si5338 Clock Generator that provides 4 output frequencies with the required logic-level, which integrates the clock design, reduces board space, and lowers the BOM parts count.