Other key parameters are lock time, phase detector frequency and tuning resolution. Lock Time is the time it takes for the final RF output frequency to settle within a certain tolerance. Wider loop bandwidth yields faster lock time. Typical lock time can range from 75µs to 200µs. Phase detector frequency is the PFD input frequency range. Since phase noise is multiplied up from the PFD by 20logN, a higher PFD frequency allows a lower divide-by-N value which improves system phase noise performance. For example doubling the PFD frequency reduces phase noise by 3dB. Tuning resolution is the frequency tuning resolution of the PLL. The integer-n PLL tuning resolution is limited by integer divider values. However, fractional-n tuning resolution is determined by fractional divider values. Fractional-n synthesizers offer designers fine tuning resolution in the hundreds of hertz.