Successive-approximation-register (SAR) ADCs represent the majority of the ADC market for medium-to high-resolution ADCs. The analog input voltage V_IN is held on a sample and hold buffer, and compared to the output of the voltage DAC, which was initially set to VREF/2. The comparator outputs a “1” if V_IN is greater than VDAC and “0” if it is less. Depending on the input, the SAR goes to the next bit in its register to be converted and compared again with V_IN. The cycle is repeated until every bit in the SAR has been tested. Once this is done, the conversion is complete and the N-bit digital word is available in the register.