For a pipeline ADC, the diagram here shows its general architecture. A pipeline ADC uses multiple stages and a final stage ADC to process the analog input voltage V_IN. Each stage takes V_IN and is sampled and held by a S/H buffer, while a low resolution flash ADC digitizes the same V_IN value, converts it back to an analog signal by a low resolution DAC, and then the analog output is subtracted from the original V_IN signal. The output of this subtraction operation, also known as the “residue”, is amplified for the next stage’s input. The “gained” up residue continues through the “pipeline” until it reaches the stand alone flash ADC, which resolves the last LSB bits. Because the bits from each stage are determined at different points in time, all the bits corresponding to the same sample are time-aligned before being fed to the digital-error-correction logic. The output of this stage is the final digitized signal. Note, when a stage finishes processing a sample, determining the bits, and passing the residue to the next stage, it can then start processing the next sample received from the sample-and-hold embedded within each stage. This pipelining action is the reason for the high throughput.