Communication in 1-Wire is done using the concept of time slots. A time slot is defined as the interval during which a logic 1 or 0 is written or read over the 1-Wire line. When the 1-Wire bus is idle it is driven to the supply voltage Vcc through an external resistor or integrated line driver depending on the implementation. The Master initiates a time slot by generating controlled low time duration pulses. A standard time slot lasts 60µsec while an overdrive time slot lasts 8µsec. The Slave or the Master samples the line within a specified sample window to sense logic levels during a read or write sequence.