Flip Flops

Results: 2
Series
74VHCTC74VHC
Packaging
Cut Tape (CT)Digi-Reel®Tape & Reel (TR)
Function
Master ResetSet(Preset) and Reset
Output Type
ComplementaryNon-Inverted
Number of Elements
12
Number of Bits per Element
18
Clock Frequency
110 MHz115 MHz
Max Propagation Delay @ V, Max CL
9.3ns @ 5V, 50pF11ns @ 5V, 50pF
Current - Quiescent (Iq)
2 µA4 µA
Supplier Device Package
14-TSSOP20-TSSOPB
Package / Case
14-TSSOP (0.173", 4.40mm Width)20-TSSOP (0.173", 4.40mm Width)
Stocking Options
Environmental Options
Media
Marketplace Product
2Results

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Mfr Part #
Quantity Available
Price
Series
Package
Product Status
Function
Type
Output Type
Number of Elements
Number of Bits per Element
Clock Frequency
Max Propagation Delay @ V, Max CL
Trigger Type
Current - Output High, Low
Voltage - Supply
Current - Quiescent (Iq)
Input Capacitance
Operating Temperature
Grade
Qualification
Mounting Type
Supplier Device Package
Package / Case
14-TSSOP
74VHC74FT
IC FF D-TYPE DUAL 1BIT 14TSSOP
Toshiba Semiconductor and Storage
1,983
In Stock
1 : ¥5.61000
Cut Tape (CT)
2,500 : ¥1.20522
Tape & Reel (TR)
Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Active
Set(Preset) and Reset
D-Type
Complementary
2
1
115 MHz
9.3ns @ 5V, 50pF
Positive Edge
8mA, 8mA
2V ~ 5.5V
2 µA
4 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
14-TSSOP
14-TSSOP (0.173", 4.40mm Width)
20-TSSOP
74VHC273FT
IC FF D-TYPE SNGL 8BIT 20TSSOPB
Toshiba Semiconductor and Storage
5,744
In Stock
1 : ¥7.06000
Cut Tape (CT)
2,500 : ¥1.57650
Tape & Reel (TR)
Tape & Reel (TR)
Cut Tape (CT)
Digi-Reel®
Active
Master Reset
D-Type
Non-Inverted
1
8
110 MHz
11ns @ 5V, 50pF
Positive Edge
8mA, 8mA
2V ~ 5.5V
4 µA
4 pF
-40°C ~ 85°C (TA)
-
-
Surface Mount
20-TSSOPB
20-TSSOP (0.173", 4.40mm Width)
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Flip Flops


Flip-flops are elementary digital memory devices capable of storing a single logic state or "bit" of information. They have at least two inputs; one or more to communicate the data to be stored and another to indicate the point in time to store it. Different flip-flop types such as D (delay), SR (Set-Reset), and JK respond differently to the signals presented to their inputs and can be used to implement different logical functions. They differ from latches in that they are edge sensitive devices, whose retained logic state changes only at the moment a valid clock signal is received.