This is another example using 100MHz clock cycle. The SDR device will generate 100Mbps and DDR will be 200Mbps. For DDR2, the clock cycle is doubled from DDR; hence clock becomes 200MHz, then the data rate is also doubled, achieving 400Mbps. With the next generation, DDR3, the clock frequency is double compared to DDR2 (now 400MHz for DDR3) and with data fetched always rise and fall of the clock edges the output will be 800Mbps. Applying the same principle, DDR4 clock frequency is doubled from DDR3, generating a higher performance data output.