Efficient computation of the control law is of paramount importance in all digital control systems. Control law computation is usually the dominant sample-to-out delay in the processor and is a critical factor in closed loop control performance. In general, the CPU core should compute a control algorithm in the shortest possible time. Many control algorithms are similar in form to those found in classical signal processing applications, consisting of a series of “sum-of-product” type computations. DSPs are optimised to perform these types of algorithms, which makes the C24x and C28x cores (which are essentially DSP cores) ideal for digital control. The original F240 features a 16-bit fixed point CPU core running at 20 Mhz. Later variants of the C24x increased this performance to 40 MHz, but retained the same 16-bit DSP core. The C28x Delfino class of processors features a 32-bit floating-point core running at frequencies of up to 300 MHz. The F28335, for example, is a flash based device running at 150 MHz, which represents a performance of about ten to twelve times that of the F240. The device also includes a 6-channel Direct Memory Access, DMA, engine, capable of performing block data moves between memory and peripherals without involving the CPU. With the smaller manufacturing process of the C28x family, it became possible to integrate more memory into the device. This part contains 0.5 MB of internal flash memory, or sixteen times that of the F240. It also contains 68 KB of internal RAM, which is 136 times more than the F240. The Piccolo class of processors typically run in the 40 to 80 MHz range. All are based on the 32-bit C28x core, and many also comprise a floating-point unit, similar to Delfino. A key innovation on the Piccolo design is the Control Law Accelerator, CLA. This is essentially a second C28x core, complete with floating point unit, running at the maximum speed of the device. The CLA is optimised for computation of the control law, and runs in parallel with the main CPU. This reduces sample-to-output latency and jitter, as well as doubles the CPU bandwidth. The user typically allocates real-time control algorithms to the CLA, allowing the main CPU to concentrate on supervisory or communications tasks. The Concerto family sees C28x and ARM M3 cores combined into a single device. On current devices, the C28x typically runs at 150 MHz and the M3 at 100 MHz. Each core has access to 0.5 MB of internal flash memory, up to 64 KB of internal RAM, and it’s own multi-channel DMA engine. Communication between processors is enabled by dedicated IPC, or Inter-Processor Communication RAM.