In some designs, where the on-chip oscillator in the SoC/MCU can be disabled but needs to run at Vdd >1.8 V, the VOH and VOL levels are equivalent to LVCMOS levels and the reduced swing configuration will not work. However, power savings can still be realized from using SiTime oscillators as these oscillators require lower quiescent currents during sleep mode compared to on-chip oscillators, and the higher accuracy of SiT15xx devices enables longer sleep cycles. The lower quiescent current benefit can be achieved by ordering the DCC configuration where D indicates DC coupled, the first C indicates the VOH level (which in this case is LVCMOS rail voltage) and the second C indicates the VOL level (which is LVCMOS ground level).