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WDT-Slide4

The TSCR register is used to choose which clock is used for watchdog timer counting. Each option is based upon the peripheral clock. Depending on which divisor is chosen, the timeout period can range from as short as 20.4µs or as long as 668.5ms. These numbers are calculated given a peripheral clock of 50MHz and will scale linearly. For instance, if the peripheral clock were cut in half to 25MHz, then the shortest timeout period would be 40.8µs and the longest 1337ms.

PTM Published on: 2012-04-26