At the top right of the figure one can see the different clock inputs that are available to the watchdog timer. Notice that they are all based upon the RX's peripheral clock. At the top left one can see the watchdog timer's interrupt control block. Depending on the configuration, the watchdog timer can either trigger an interrupt or output an overflow signal when a timer overflow occurs. Below the interrupt control block is the reset control block. Notice that the RSTCSR register is feeding into this block. This register controls whether or not the watchdog timer sends a reset signal to the MCU when a timer overflow occurs.