To understand the detailed timing of the interrupt generation, the timing of the counter CMCNT needs to be explained. Once per prescalar countdown, a count clock is generated for one peripheral clock period. It is this count clock that causes the counter CMCNT to be incremented. The compare match signal is generated when counter CMNT is incremented by the count clock after it has matched the compare match CMCOR register. The period of the interrupt signal is therefore CMCOR+1 cycle of the count clock. On the peripheral clock edge after the compare match signal is generated, the counter is reset and the CMI signal is sent to the interrupt control unit. The CMI signal can generate an interrupt to the CPU core, trigger a DTC or DMAC transfer or be polled by software. This particular behavior is controlled by the configuration of the interrupt control unit.